1. Field of the Invention
The present invention relates to an inspection method and an inspection apparatus using an electron beam, both of which inspect a sample such as a semiconductor device having micro-fabricated patterns, a substrate, a photomask (a mask having patterns formed thereon, which is used for exposing patterns on a substrate), and a liquid crystal plate.
2. Description of the Related Art
Semiconductor devices such as memories and microcomputers used for computers, etc. are manufactured through the repetition of transcription processes such as exposing, lithographing, or etching patterns such as circuits, which are formed on photomasks. In the manufacturing process of semiconductor devices, the manufacturing yield is greatly affected by several factors. These include whether or not the results of the lithography process, etching process, or other processes involved are satisfactory. Yield is also affected by the presence or absence of foreign matter of the like. Therefore, in order to detect early or in advance the occurrence of abnormalities or defects, patterns on a semiconductor wafer are inspected at the end of each manufacturing process.
As one example of a method for inspecting defects present in a pattern on a semiconductor wafer, an optical visual inspection apparatus has been put into practice, wherein the comparison of patterns is performed using optical images obtained through light irradiation of a semiconductor wafer. However, as circuits have miniaturized (micro) patterns and complicated shapes, and as materials used for circuits have become diversified, it is difficult to detect these defects using optical images. Thus, a method and an apparatus for inspecting a pattern using an electron beam image that has higher resolution than an optical image have been put into practice.
Known are technologies disclosed, for example, in JP Patent Publication (Kokai) No. 59-192943, JP Patent Publication (Kokai) No. 5-258703, Sandland, et al., “An electron-beam inspection system for x-ray mask production,” J. Vac. Sci. Tech. B, Vol. 9, No. 6, pp. 3005-3009 (1991), Meisburger, et al., “Requirements and performance of an electron-beam column designed for x-ray mask inspection,” J. Vac. Sci. Tech. B, Vol. 9, No .6, pp. 3010-3014 (1991), Meisburger, et al., “Low-voltage electron-optical system for the high-speed inspection of integrated circuits,” J. Vac. Sci. Tech. B, Vol. 10, No. 6, pp. 2804-2808 (1992), Hendricks, et al., “Characterization of a New Automated Electron-Beam Wafer Inspection System,” and SPIE Vol. 2439, pp. 174-183 (Feb. 20-22, 1995).
In order to achieve high throughput and highly accurate inspections in line with the increase of wafer bore diameter and the miniaturization of circuit patterns, there is a need to obtain a high SN image at very high speeds. To this end, the number of electrons emitted through the use of a larger beam, with a current 1,000 times or more (100 nA or more) greater than that of an ordinary scanning electron microscope (hereinafter referred to as an SEM), should be preserved to ensure the maintenance of a high SN ratio. Further, it is essential to detect secondary electrons generated from a substrate and reflected electrons at high speeds and with high efficiency.
Furthermore, in order to prevent a semiconductor substrate with a insulating film such as a resist from being affected by charging, it is necessary to apply a low accelerated electron beam of 2 keV or less. This technology is disclosed in the “Electron/Ion beam handbook (2nd edition),” edited by the 132nd Committee of Japan Society for the Promotion of Science, pp. 622-623, Nikkan Kogyo Shimbun (1986). However, the use of the low accelerated electron beam with a large current generates aberrations due to the space charge effect, and thereby high-resolution observation has been difficult.
As a method for solving this problem, a technology wherein a highly accelerated electron beam is decelerated directly before a sample and is applied to the sample substantially as a low-speed accelerated electron beam is known. Such technology is disclosed in, for example, JP Patent Publication (Kokai) No. 2-142045 and JP Patent Publication (Kokai) No. 6-139985.
With respect to an inspection apparatus using the above SEM, the following problems have yet to be solved.
One problem is that detailed evaluation is impossible because the presence of defects is digitally judged as being 0 or 1, and during this period analog judgment cannot be performed. Taking a non-opening defect of a plug hole bottom as an example, this means that it is conventionally judged to be conductive or non-conductive, but in contrast there also exists an intermediate, semi-conductive state. However, a plug is originally required to permit low resistance and ohmic connections among levels of wirings. In view of this point, it can be said that a detailed analog evaluation should be conducted using the resistance.
Further, refresh defects of DRAMs, transistor leakage defects of flash memories, or the like, though they are categorized as the same type of electric characteristic defects, are caused by a micro leakage current of a pn junction, and these defects are difficult to detect even with an SEM inspection apparatus. JP Patent Publication (Kokai) No. 2002-9121 discloses attempts to detect the above defects by intermittently applying an electron beam in a condition where a junction is charged in a reverse biased state, and detecting the defect as an electric potential contrast image using a state where the charge is relaxed through a junction leakage current.
However, in this method, since the irradiation of the electron beam at the same location is repeated many times, it is necessary to move a wafer in a step-and-repeat manner. Therefore, when stationary time of a stage mechanism or time lost through stage control is taken into consideration, a problem arises, in which the throughput, evaluated in terms of the time required for one semiconductor substrate, deteriorates.